1. Field of the Invention
The present invention relates to an ultra high voltage MOS transistor device, and more particularly, to an ultra high voltage lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor device.
2. Description of the Prior Art
Double-diffused MOS (DMOS) transistor devices have drawn much attention in power devices having high voltage capability. The conventional DMOS transistor devices are categorized into vertical double-diffused MOS (VDMOS) transistor device and lateral double-diffused MOS (LDMOS) transistor device. Having advantage of higher operational bandwidth, higher operational efficiency, and convenience to be integrated with other integrated circuit due to its planar structure, LDMOS transistor devices are widely used in high operational voltage environment such as CPU power supply, power management system, AC/DC converter, and high-power or high frequency (HF) band power amplifier. The essential feature of LDMOS transistor device is a lateral-diffused drift region with low dope concentration and large area. The drift region is used to alleviate the high voltage between the drain and the source, therefore LDMOS transistor device can have higher breakdown voltage.
Please refer to FIG. 1, which is a cross-section view of a conventional LDMOS transistor device. As shown in FIG. 1, the conventional LDMOS transistor device 10 having a P-type well 20, a source 14 and a P-type heavily doped region 22 formed in the P-type well 20, a gate 16 and a drain 18 is formed on a semiconductor substrate 12. The drain 18 is an N-type heavily doped region formed in an N-type well 30, which is the drift region as mentioned above. The dope concentration and length of the drift region affects the breakdown voltage and the ON-resistance (RON) of LDMOS transistor device 10. The conventional LDMOS transistor device 10 further includes a P-type doped region 32 formed in the N-type well 30 for increasing the breakdown voltage of LDMOS transistor device 10. The gate 16 of LDMOS transistor device 10 is positioned on a gate dielectric layer 40 and extended to cover a portion of a field oxide layer 42.
Please still refer to FIG. 1. It is well-known that LDMOS transistor device 10 is used under high operational voltage environment, when the inductive voltage generated in the semiconductor substrate 12 during the operation is sufficiently large, a forward bias is generated between the semiconductor substrate 12 and the source 14, and a parasite bipolar junction transistor (BJT) is turned on. Thus the snap back voltage of the drain 18 is decreased and current flow from the drain 18 to the source 14 is abruptly increased. This so-called snap-back phenomenon makes LDMOS transistor device 10 defective.
Secondly, the P-type doped region 32 formed in the N-type well 30 is to form a fully-depleted region in the drift region, and the fully-depleted region has to be formed before the device reaches the breakdown voltage. Conventionally, the prior art reduces the dope concentration of the N-type well 30 for accelerating the formation of the fully-deleted region. However, this method suffers higher RON due to the low dope concentration of the N-type well 30.
Therefore, a LDMOS transistor device that is able to realize high breakdown voltage and low RON, and to avoid the abovementioned problem is still in need.